Input structures for protecting the gate oxide of MOS (Metal Oxide Semiconductor) transistors connected to input pads are widely used in Integrated Circuits (IC). Such an input structure typically receives the voltage applied to an IC pad and supplies a reduced voltage to the IC thereby ensuring that the gate-to-source and gate-to-drain voltages of the IC transistors do not exceed a maximum allowable limit.
Currently known input structures fail to provide adequate protection for the gate oxide when no power is supplied to the IC and yet the pads of the IC continue to receive power. The problem is further compounded when ICs manufactured using deep submicron (e.g. 0.25 .mu.m) CMOS technologies--where the gate-to-source and gate-to-drain voltages of an MOS transistor must remain below 3.5 volts--are used in a system requiring 5.5 volts to operate. When used in such a system, the IC must be able to withstand the application of 5.5 volts to its pads both when the power supply to the IC is on and when it is off.
FIG. 1 shows a known input structure 10. Input structure 10 receives voltage Vin on pad 12 and supplies voltage Vout at the output terminal of inverter 22. Input structure 10 suffers from contention, as described below. To force the voltage Vout to a low level when no voltage is applied to pad 12, a user may place an external resistor (not shown) across pad 12 and the system ground. When such a resistor is used and a hiqh voltage is applied to pad 12 before tri-stating pad 12, PMOS transistor 18 turns on, pulling node N1 to a high voltage. At the same time, the external resistor pulls node N1 to ground. Therefore, a contention develops between PMOS transistor 18 and the external transistor. If the pull-up capability of transistor 18 is greater than the pull-down capability of the external resistor, voltage Vout remains at the high level.
FIG. 2 shows known input structure 30. Input structure 30 does not have the contention problem of input structure 10 but consumes too much DC power because PMOS transistor 36 is never completely turned off.
FIG. 3 shows known input structure 50. Input structure 50 does not have the contention problem of input structure 10 nor does it have the excessive power consumption of input structure 30 but it suffers from a major disadvantage. To avoid the natural hysterisis in input structure 50, PMOS transistors 56 and 58 must be made large to meet the required threshold high and low specifications and which, in turn, makes the input structure undesirably slow.
In yet other known input structures (not shown) the MOS transistors are formed using thick gate oxides to protect against the pad over-voltage when the supply voltage is tuned off. Therefore, an IC containing such an input structure requires a manufacturing process that supports both regular and thick gate oxide MOS transistors and is thus expensive.
Therefor, a need exists for an input structure for protecting the internal circuitry of an IC when the pads of the IC continue to receive power but the supply power to the IC is turned off, and which overcomes the known problems of the existing input structures discussed above.